The invention relates generally to the field of nonvolatile semiconductor memories, and more specifically to the field of floating gate programmable memories.
Floating gate memory devices such as flash memories include an array of electrically programmable and electrically erasable memory cells. Typically, each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor, including a floating gate interposed between a control (input) gate and a channel. A layer of high-quality tunnel oxide used as gate oxide separates the transistor channel and the floating gate, and an oxide-nitride-oxide (ONO) dielectric stack separates the floating gate from the control gate. The ONO stack typically comprises a layer of silicon nitride (Si3N4) interposed between an underlying layer and an overlying layer of silicon dioxide (SiO2). The underlying layer of SiO2 is typically grown on the first doped polycrystalline silicon (poly) layer. The nitride layer is deposited over the underlying oxide layer, and the overlying oxide layer can be either grown or deposited on the nitride layer. The ONO layer maximizes the capacitive coupling between the floating gate and the control gate and minimizes the leakage of current through the film.
In order to program a flash cell the drain region and the control gate are raised to predetermined potentials above a potential applied to the source region. For example 12 volts are applied to the control gate, 0.0 volts are applied to the source, and 6.0 volts are applied to the drain. These voltages produce xe2x80x9chot electronsxe2x80x9d which are accelerated from the substrate across the gate oxide layer to the floating gate. To erase a flash cell a high positive potential, for example 12 volts, is applied to the source region, the control gate is grounded, and the drain is allowed to float. These voltages are applied for a timed period, and the longer the period the more the cell becomes erased. A strong electric field develops between the floating gate and the source region, and negative charge is extracted from the floating gate across the tunnel oxide to the source region, for example by Fowler-Nordheim tunneling.
The bottom and top silicon dioxide layers in the ONO stack with current technology are typically about 40 xc3x85 thick and the silicon nitride layer is typically about 100 xc3x85 thick. This silicon dioxide layer passivates any pinhole defects in the nitride, which are common with nitride layers. Oxidizing the nitride layer to form the overlying silicon dioxide layer has improved pinhole passivation over deposited oxide layers. Further, the thickness of the top silicon dioxide layer is easier to control when grown rather than deposited. However, because the Sixe2x80x94N bond is very stable and silicon nitride has a low availability of unreacted silicon, it is difficult and time consuming to oxidize nitride at lower temperatures. Thus the nitride oxidation process is typically performed at relatively high temperatures for example at 950xc2x0 C. or higher. If the oxidation temperature is lowered to 900xc2x0 C. or below, it will require at least 120 minutes to form a 40 xc3x85 film.
Increased processing temperatures, such as those for growing silicon dioxide on nitride, are known to cause various problems in the field of semiconductor device manufacturing, and failures related to flash memory devices in particular. For example, increased temperatures are known to stress the interfaces of previously grown films such as the tunnel oxide and field oxide. These films then become more prone to charge trapping, which degrades the operation of the device.
A method for forming a semiconductor device, particularly a flash memory device, which allows for the improved formation of a silicon dioxide layer over a layer which resists oxide formation, such as a nitride layer in an ONO stack, would be desirable.
The present invention provides a new method for forming an interlayer dielectric, for example an oxide-nitride-oxide (ONO) layer between a floating gate layer and a control gate layer, which allows for the growth of an oxide layer over a nitride layer at decreased temperatures compared with conventional processes. In accordance with one embodiment of the invention a first oxide layer is grown or deposited over a floating gate poly layer, then a nitride layer is formed over the first oxide layer. During the nitride formation, at least an upper portion of the nitride layer is siliconized. Finally, a second oxide layer is grown over the nitride layer. The siliconized (silicon-rich) nitride layer enhances the formation of the second oxide layer and allows for its growth at lower temperatures than conventional processes. Growing the second oxide layer rather than depositing the second oxide layer provides improved healing of pinhole defects in the nitride layer. Growing the second oxide layer at lower temperatures than can be done with conventional processing reduces problems associated with a tunnel oxide layer of a flash memory device and reduces other temperature-induced failures.
In a second embodiment a pure silicon layer, such as a thin polycrystalline silicon layer is formed over a nitride layer in the ONO stack. The polycrystalline silicon layer is more easily oxidized than the nitride layer, thereby decreasing processing time.